`include "ascon_define.v"

module `ROUND_PL
(
     input                           [`XI_W-1:0] x0_i,
     input                           [`XI_W-1:0] x1_i,
     input                           [`XI_W-1:0] x2_i,
     input                           [`XI_W-1:0] x3_i,
     input                           [`XI_W-1:0] x4_i,

     output                           [`S_W-1:0] s_o
);

//外接口定义
wire                                 [`XI_W-1:0] x0_w;
wire                                 [`XI_W-1:0] x1_w;
wire                                 [`XI_W-1:0] x2_w;
wire                                 [`XI_W-1:0] x3_w;
wire                                 [`XI_W-1:0] x4_w;

wire                                  [`S_W-1:0] s_w;
//接口信号 定义
wire                                 [`XI_W-1:0] x0_p_w;
wire                                 [`XI_W-1:0] x1_p_w;
wire                                 [`XI_W-1:0] x2_p_w;
wire                                 [`XI_W-1:0] x3_p_w;
wire                                 [`XI_W-1:0] x4_p_w;

//接口信号 与外接口连接

assign x0_w             = x0_i;
assign x1_w             = x1_i;
assign x2_w             = x2_i;
assign x3_w             = x3_i;
assign x4_w             = x4_i;

assign s_o              = s_w;

assign x0_p_w           = {x0_w[18:0],x0_w[63:19]} ^ x0_w ^ {x0_w[27:0],x0_w[63:28]};
assign x1_p_w           = {x1_w[60:0],x1_w[63:61]} ^ x1_w ^ {x1_w[38:0],x1_w[63:39]};
assign x2_p_w           = {x2_w[0:0] ,x2_w[63:1] } ^ x2_w ^ {x2_w[5:0] ,x2_w[63:6] };
assign x3_p_w           = {x3_w[9:0] ,x3_w[63:10]} ^ x3_w ^ {x3_w[16:0],x3_w[63:17]};
assign x4_p_w           = {x4_w[6:0] ,x4_w[63:7] } ^ x4_w ^ {x4_w[40:0],x4_w[63:41]};

`ROUND_MERGE
u_round_merge
     (
     .x0_i                             (x0_p_w                                 ),
     .x1_i                             (x1_p_w                                 ),
     .x2_i                             (x2_p_w                                 ),
     .x3_i                             (x3_p_w                                 ),
     .x4_i                             (x4_p_w                                 ),

     .s_o                              (s_w                                    )
     );

endmodule